Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
Read operations usually are performed on floating gate memory cells using sensing amplifiers. A sensing amplifier for this purpose is disclosed in U.S. Pat. No. 5,386,158 (the “'158 Patent”), which is incorporated herein by reference for all purposes. The '158 Patent discloses using a reference cell that draws a known amount of current. The '158 Patent relies upon a current mirror to mirror the current drawn by the reference cell, and another current mirror to mirror the current drawn by the selected memory cell. The current in each current mirror is then compared, and the value stored in the memory cell (e.g., 0 or 1) can be determined based on which current is greater.
Another sensing amplifier is disclosed in U.S. Pat. No. 5,910,914 (the “'914 Patent”), which is incorporated herein by reference for all purposes. The '914 Patent discloses a sensing circuit for a multi-level floating gate memory cell or MLC, which can store more than one bit of data. It discloses the use of multiple reference cells that are utilized to determine the value stored in the memory cell (e.g., 00, 01, 10, or 11). Current mirrors are utilized in this approach as well.
The current mirrors of the prior art utilize PMOS transistors. One characteristic of PMOS transistors is that a PMOS transistor can only be turned “on” if the voltage applied to the gate is less than the voltage threshold of the device, typically referred to as VTH. One drawback of using current mirrors that utilize PMOS transistors is that the PMOS transistor causes a VTH drop. This hinders the ability of designers to create sensing amplifiers that operate at lower voltages.
Another drawback of the prior art design is that PMOS transistors are relatively slow when the gate transitions from high to low (i.e., when the PMOS transistor turns on). This results in delay of the overall sensing amplifier.
What is needed is an improved sensing circuit that operates using a lower voltage supply than in the prior art.
What is further needed is an improved sensing circuit where the voltage supply can be turned off when not in use to save power, but where the sensing circuit can become operational without a significant timing penalty once the voltage supply is turned back on.